Description
256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Specification of 256Mb (16Mx16bit) Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of .
and is subject to change without notice.
Features
* SUMMARY
* Mobile DDR SDRAM
clock cycle
* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM)
- Double data rate architecture: two data transfer per
* Mobile DDR SDRAM INTERFACE
- x16 bus width - Multiple
Applications
* which use the battery such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 4,194,304 x16. The HYNIX H5MS2562JFR series uses a double-data-rate architecture to achieve high-speed operation. The double da
