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HD74HCT620 - Octal Bus Transceivers (with inverted 3-state outputs)/

General Description

This octal transceiver is designed for asynchronous two-way communication between data buses.

The control function implementation allows for maximum flexibility in timng.

Key Features

  • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (Bus to Bus) = 15 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HCT620/HD74HCT623 Function Table Enable Input GBA L H H L GAB L H L H Operation HD74HCT620 B data to A bus A dat.

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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HCT623 Octal Bus Transceivers (with inverted 3-state outputs)/
HD74HCT640 Octal Bus Transceivers (with 3-state outputs)
HD74HCT643 Octal Bus Transceivers (with 3-state outputs)
HD74HCT688 8-bit Magnitude Comparator
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74HCT620/HD74HCT623 Octal Bus Transceivers (with inverted 3-state outputs)/ Octal Bus Transceivers (with 3-state outputs) Description This octal transceiver is designed for asynchronous two-way communication between data buses. The control function implementation allows for maximum flexibility in timng. This device allows data transmission from A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the enable inputs (GBA and GAB). The enable inputs can be used to disable the device so that the buses are affectively isolated. The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of GBA and GAB. Each output reinforces its input in this transceiver configuration.