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GS8342D08E-300 - 36Mb SigmaQuad-II Burst

Download the GS8342D08E-300 datasheet PDF. This datasheet also covers the GS8342D08E-333 variant, as both devices belong to the same 36mb sigmaquad-ii burst family and are provided as variant models within a single manufacturer datasheet.

Description

Table Symbol SA NC R W BW0 BW3 NW0 NW1 K K C C TMS TDI TCK TDO VREF ZQ Qn Dn Doff CQ CQ VDD VDDQ VSS Note: NC = Not Connected to die or any other pin Description Synchronous Address Inputs No Connect Synchronous Read Synchronous Write Synchronous Byte Writes Nybble Write Control Pin

Features

  • Simultaneous Read and Write SigmaQuad™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • Burst of 4 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully coherent read and write pipelines.
  • ZQ pin for programmable output drive strength.
  • IEEE 1149.1 JTAG-co.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8342D08E-333_GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8342D08E-300
Manufacturer GSI Technology
File Size 2.39 MB
Description 36Mb SigmaQuad-II Burst
Datasheet download datasheet GS8342D08E-300 Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS8342D08E-333 36Mb SigmaQuad-II Burst
GS8342D08E-167 36Mb SigmaQuad-II Burst
GS8342D08E-200 36Mb SigmaQuad-II Burst
GS8342D08E-250 36Mb SigmaQuad-II Burst
GS8342D08AE 36Mb SigmaQuad-II Burst of 4 SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Preliminary GS8342D08/09/18/36E-333/300/250/200/167 www.DataSheet4U.com 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 4 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available • Pin-compatible with present 9Mb and 18Mb and future 72Mb and 144Mb devices 36Mb SigmaQuad-II Burst of 4 SRAM 167 MHz–333 MHz 1.8 V VDD 1.
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