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GTLP16T1655 - 16-Bit LVTTL/GTLP Universal Bus Transceiver

Description

The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation.

It allows for transparent, latched and clocked modes of data transfer.

Features

  • s Bidirectional interface between GTLP and LVTTL logic levels s Variable Edge Rate Control pin to select desired edge rate on the GTLP backplane (VERC ) s Partitioned as two 8-Bit transceivers with individual latch timing and output control but with a common clock. s Power up/down high impedance for live insertion. s External pin to pre-condition I/O capacitance to high state s Bus-hold data inputs on the A-Port eliminates the need for external pull-up resistors on unused inputs s LVTTL compatib.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver August 1998 Revised April 2000 GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver General Description The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3.
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