CD4027BC Datasheet (Fairchild Semiconductor) - Dual J-K Master/Slave Flip-Flop

CD4027BC, Dual J-K Master/Slave Flip-Flop

The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors.

Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs.

These flip-flops are edge sensitive to the cloc

CD4027BC Features

* s Wide supply voltage range: s High noise immunity: 3.0V to 15V 0.45 VDD (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s Low power: 50 nW (typ.) s Medium speed operation: 12 MHz (typ.) with 10V supply Ordering Code: Order Number CD4027BCM CD4027BCN Package Number