QL2009-0PB256I, QL2 - 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility

QL2009-0PB256I Datasheet Preview — This datasheet PDF includes multiple part numbers: QL2009-0PB256I, QL2. Please refer to the document for exact specifications by model.

Datasheet Details

Part number	QL2009-0PB256I, QL2
Manufacturer	ETC
File Size	272.83 KB
Description	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
Datasheet	QL2-009.pdf
Note	This datasheet PDF includes multiple part numbers: QL2009-0PB256I, QL2. Please refer to the document for exact specifications by model.

QL2009-0PB256I Product details

Description

Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-drive input Input/Output pin Power supply pin Ground pin Description Hold HIGH during normal operation.

Features

-3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3-35 QL2009.

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Published: Apr 16, 2005 |