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P3R1GE3JGF - 1G bits DDR2 SDRAM

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P3R1GE3JGF 1G bits DDR2 SDRAM by Deutron Electronics - Datasheet Preview — Datasheet preview – P3R1GE3JGF

Datasheet Details

Part number	P3R1GE3JGF
Manufacturer	Deutron Electronics
File Size	2.91 MB
Description	1G bits DDR2 SDRAM
Datasheet	P3R1GE3JGF Datasheet
Additional preview pages of the P3R1GE3JGF datasheet.

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Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

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