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CY7C1992BV18 - 1.8V Synchronous Pipelined SRAM

Download the CY7C1992BV18 datasheet PDF. This datasheet also covers the CY7C1392BV18 variant, as both devices belong to the same 1.8v synchronous pipelined sram family and are provided as variant models within a single manufacturer datasheet.

Features

  • 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36).
  • 300 MHz clock for high bandwidth.
  • 2-word burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1392BV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C199 32K x 8 Static RAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1392BV18, CY7C1992BV18 CY7C1393BV18, CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Synchronous internally self-timed writes ■ 1.8V core power supply with HSTL inputs and outputs ■ Variable drive HSTL output buffers ■ Expanded HSTL output voltage (1.
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