CY7C1311KV18 Datasheet - Cypress Semiconductor

CY7C1311KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture

CY7C1311KV18 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 333-MHz clock for high bandwidth

* Four-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz

Datasheet Details

CY7C1311KV18

Cypress Semiconductor

657.31 KB

18-mbit qdr ii sram four-word burst architecture.

📁 Related Datasheet

CY7C1311AV18 (CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture (Cypress Semiconductor)

CY7C1311BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture (Cypress Semiconductor)

CY7C1311CV18 (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture (Cypress Semiconductor)

CY7C1311JV18 (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture (Cypress Semiconductor)

CY7C131 1K x 8 Dual-Port Static RAM (Cypress Semiconductor)

CY7C1310BV18 1.8V Synchronous Pipelined SRAM (Cypress Semiconductor)

CY7C1312BV18 1.8V Synchronous Pipelined SRAM (Cypress Semiconductor)

CY7C1312KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture (Cypress Semiconductor)

TAGS

CY7C1311KV18 Distributor