EP1810 - EPLD

Product Overview

Altera

Part number	EP1810
Manufacturer	Altera
File Size	657.80 KB
Description	EPLD
Datasheet	EP1810 Datasheet
Additional preview pages of the EP1810 datasheet.

The Altera ClassicTM device family offers a solution to high-speed, lowpower logic integration.

Classic ® EPLD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s Device erasure and reprogramming with non-volatile EPROM configuration elements s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz s 24 to 68 pins available in dual in-line package (DIP), plastic J-lead chip carrier (PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages s Programmable security bit for protec.

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Published: Nov 11, 2019 |