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AS7C1026C 5V 64K x 16 CMOS SRAM

AS7C1026C Description

September 2006 A AS7C1026C ® 5 V 64K X 16 CMOS SRAM * Industrial (-40o to 85oC) temperature * Organization: 65,536 words × 16 bits <.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE).

AS7C1026C Features

* JEDEC standard packaging
* ESD protection > _ 2000 volts - 44-pin 400 mil SOJ - 44-pin TSOP 2-400 Pin arrangement 44-Pin SOJ (400 mil), TSOP 2 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2

AS7C1026C Applications

* When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). The AS7C1026C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536

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📌 All Tags

64K CMOS SRAM Alliance Semiconductor
Alliance Semiconductor AS7C1026C-like datasheet