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HEF4014B-Q100 - 8-bit static shift register

Description

The HEF4014B-Q100 is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (D0 to D7).

It has a synchronous serial data input (DS), a synchronous parallel enable input (PE) and a LOW-to-HIGH edge-triggered clock input (CP).

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 3).
  • Specified from -40 °C to +85 °C.
  • Tolerant of slow clock rise and fall times.
  • Fully static operation.
  • 5 V, 10 V, and 15 V parametric ratings.
  • Standardized symmetrical output characteristics.
  • ESD protection:.
  • MIL-STD-833, method 3015 exceeds 2000 V.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω).

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Datasheet preview – HEF4014B-Q100

Datasheet Details

Part number HEF4014B-Q100
Manufacturer nexperia
File Size 200.06 KB
Description 8-bit static shift register
Datasheet download datasheet HEF4014B-Q100 Datasheet
Additional preview pages of the HEF4014B-Q100 datasheet.

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Full PDF Text Transcription

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HEF4014B-Q100 8-bit static shift register Rev. 2 — 17 October 2018 Product data sheet 1. General description The HEF4014B-Q100 is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (D0 to D7). It has a synchronous serial data input (DS), a synchronous parallel enable input (PE) and a LOW-to-HIGH edge-triggered clock input (CP). It also has buffered parallel outputs from the last three stages (Q5 to Q7). Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH transition of CP. Each register stage is of a D-type master-slave flip-flop type. When PE is HIGH, data is loaded into the register from D0 to D7 on the LOW-to-HIGH transition of CP. When PE is LOW, data is shifted to the first position from DS.
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