Datasheet4U Logo Datasheet4U.com

74LVT04 - Hex inverter

General Description

The 74LVT04 is a hex inverter.

This device is fully specified for partial power down applications using IOFF.

The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Key Features

  • Wide supply voltage range from 2.7 to 3.6 V.
  • Overvoltage tolerant inputs to 5.5 V.
  • BiCMOS high speed and output drive.
  • Direct interface with TTL levels.
  • No bus current loading when output is tied to 5 V bus.
  • Power-up 3-state.
  • IOFF circuitry provides partial Power-down mode operation.
  • Latch-up performance exceeds 500 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74LVT04 3.3V Hex inverter NXP
74LVT00 3.3V Quad 2-input NAND gate NXP
74LVT02 3.3V Quad 2-input NOR gate NXP
74LVT08 3.3V Quad 2-input AND gate NXP
74LVT10 3.3V Triple 3-input NAND gate NXP

Other Datasheets by Nexperia

Part Number Description
74LVT04-Q100 Hex inverter
74LVT02 3.3V Quad 2-input NOR gate
74LVT08 3.3V Quad 2-input AND gate
74LVT125 3.3V quad buffer
74LVT126 quad buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74LVT04 3.3 V Hex inverter Rev. 4 — 12 August 2021 Product data sheet 1. General description The 74LVT04 is a hex inverter. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 2.7 to 3.6 V • Overvoltage tolerant inputs to 5.5 V • BiCMOS high speed and output drive • Direct interface with TTL levels • No bus current loading when output is tied to 5 V bus • Power-up 3-state • IOFF circuitry provides partial Power-down mode operation • Latch-up performance exceeds 500 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.