74HC112D datasheet, flip-flop equivalent, nexperia

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Features and benefits

* Input levels:
* For 74HC112: CMOS level
* For 74HCT112: TTL level
* Asynchronous set and reset
* Specified in compliance with JEDEC standard no. 7A .

Description

The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inpu.

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