SN74SSQE32882 Datasheet - Texas Instruments

SN74SSQE32882 28-BIT TO 56-BIT REGISTERED BUFFER

ORDERING INFORMATION This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 Registered DIMMs up to DDR3-1333 with VDD of 1.5 V. All inputs are 1.5-V, CMOS-compatible. All outputs are 1.5-V CMOS drivers optimized t.

SN74SSQE32882 Features

* 1

* 2 JEDEC SSTE32882 Compliant

* 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 DIMMs

* Chip Select Inputs Prevent Data Outputs from Changing State and Minimize System Power Consumption

* 1.5-V Phase Lock Loop Clock Driver Buffers One Diffe

SN74SSQE32882 Datasheet (831.58 KB)