1
*2 JEDEC SSTE32882 Compliant
* 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 DIMMs
* Chip Select Inputs Prevent Data Outputs fr.

* DDR3 Registered DIMMs up to DDR3-1333
* Single-, Dual- and Quad-Rank RDIMM DESCRIPTION/ORDERING INFORMATION Th.

ORDERING INFORMATION This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 Registered DIMMs up to DDR3-1333 with VDD of 1.5 V. All inputs are 1.5-V, CMOS-compatib.

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