SN74LV125AT gates equivalent, quadruple bus buffer gates.
* Inputs Are TTL-Voltage Compatible
* 4.5-V to 5.5-V VCC Operation
* Typical tpd of 3.8 ns at 5 V
* Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 5 .
using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is .
ORDERING INFORMATION
The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state .
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