900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






etcTI

SN74AHC138 Datasheet Preview

SN74AHC138 Datasheet

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

No Preview Available !

SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258L − DECEMBER 1995 − REVISED JULY 2003
D Operating Range 2-V to 5.5-V VCC
D Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
D Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54AHC138 . . . J OR W PACKAGE
SN74AHC138 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
SN74AHC138 . . . RGY PACKAGE
(TOP VIEW)
SN54AHC138 . . . FK PACKAGE
(TOP VIEW)
A
B
C
G2A
G2B
G1
Y7
GND
1
2
3
4
5
6
7
8
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
1
8
16
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9
C
G2A
NC
G2B
G1
3 2 1 20 19
4 18
5 17
6 16
7 15
8 14
9 10 11 12 13
Y1
Y2
NC
Y3
Y4
description/ordering information
NC − No internal connection
The ’AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing
applications that require very short propagation-delay times. In high-performance memory systems, these
decoders can be used to minimize the effects of system decoding. When employed with high-speed memories
utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are
less than the typical access time of the memory. This means that the effective system delay introduced by the
decoders is negligible.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY
Tape and reel SN74AHC138RGYR
HA138
PDIP − N
Tube
SN74AHC138N
SN74AHC138N
SOIC − D
Tube
Tape and reel
SN74AHC138D
SN74AHC138DR
AHC138
−40°C to 85°C
SOP − NS
Tape and reel SN74AHC138NSR
AHC138
SSOP − DB
Tape and reel SN74AHC138DBR
HA138
TSSOP − PW
Tube
Tape and reel
SN74AHC138PW
SN74AHC138PWR
HA138
TVSOP − DGV
Tape and reel SN74AHC138DGVR
HA138
CDIP − J
Tube
SNJ54AHC138J
SNJ54AHC138J
−55°C to 125°C CFP − W
Tube
SNJ54AHC138W
SNJ54AHC138W
LCCC − FK
Tube
SNJ54AHC138FK
SNJ54AHC138FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1




etcTI

SN74AHC138 Datasheet Preview

SN74AHC138 Datasheet

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

No Preview Available !

SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258L − DECEMBER 1995 − REVISED JULY 2003
description/ordering information (continued)
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XHXXXXHHHHHHHH
XXHXXXHHHHHHHH
L XXXXXHHHHHHHH
HL L L L L LHHHHHHH
HL L L LHHLHHHHHH
HL L LHLHHLHHHHH
HL L LHHHHHLHHHH
HL LHL LHHHHLHHH
HL LHLHHHHHHLHH
HL LHHLHHHHHHLH
HL LHHHHHHHHHHL
logic diagram (positive logic)
A1
15
Y0
14
Y1
Select
Inputs
B2
3
C
13
Y2
12
Y3
11 Y4
Data
Outputs
10
Y5
Enable
Inputs
G2A
G2B
G1
4
5
6
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
9
Y6
7 Y7
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN74AHC138
Description 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
Maker etcTI
Total Page 29 Pages
PDF Download

SN74AHC138 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 SN74AHC132 Quadruple Positive-NAND Gates
etcTI
2 SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
etcTI
3 SN74AHC139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
etcTI





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy