SCLS259L – DECEMBER 1995 – REVISED JUNE 2013
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
Check for Samples: SN74AHC139, SN54AHC139
• Operating Range 2-V to 5.5-V
• Designed Specifically for High-Speed Memory
Decoders and Data-Transmission Systems
• Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception
• Latch-Up Performance Exceeds 250 mA Per
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN54AHC139 . . . J or W PACKAGE
SN74AHC139 . . . D,DB,DGV,N,NS
OR PW PACKAGE
SN74AHC139 . . . RGY PACKAGE
SN54AHC139 . . . FKP ACKAGE
3 2 1 20 19
9 10 11 12 13
NC − No internal connection
The ’AHC139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 2-V to 5.5-V VCC operation.
These devices are designed to be used in high-performance memory-decoding or data-routing applications
requiring very short propagation delay times. In high-performance memory systems, these decoders can be used
to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit,
the delay times of these decoders and the enable time of the memory usually are less than the typical access
time of the memory. This means that the effective system delay introduced by the decoders is negligible.
G Y0 Y1 Y2
L L L LHH
LH LHH L
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
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