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SN65LVDS17 - 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

Download the SN65LVDS17 datasheet PDF. This datasheet also covers the SN65LVDS16 variant, as both devices belong to the same 2.5-v/3.3-v oscillator gain stage/buffers family and are provided as variant models within a single manufacturer datasheet.

General Description

These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems.

Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.

Key Features

  • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs.
  • Clock Rates to 2 GHz.
  • 140-ps Output Transition Times.
  • 0.11 ps Typical Intrinsic Phase Jitter.
  • Less than 630 ps Propagation Delay Times.
  • 2.5-V or 3.3-V Supply Operation.
  • 2-mm × 2-mm Small-Outline No-Lead Package.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SN65LVDS16-etcTI.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.ti.com SN65LVDS16, SN65LVP16 SN65LVDS17, SN65LVP17 SLLS625B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS FEATURES • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs • Clock Rates to 2 GHz – 140-ps Output Transition Times – 0.11 ps Typical Intrinsic Phase Jitter – Less than 630 ps Propagation Delay Times • 2.5-V or 3.3-V Supply Operation • 2-mm × 2-mm Small-Outline No-Lead Package APPLICATIONS • PECL-to-LVDS Translation • Clock Signal Amplification DESCRIPTION These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems.