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Reference Design
SN65LVDS100, SN65LVDT100, SN65LVDS101, SN65LVDT101
SLLS516E – AUGUST 2002 – REVISED JULY 2015
SN65LVDx10x Differential Translator/Repeater
1 Features
•1 Designed for Signaling Rates ≥ 2 Gbps • Total Jitter < 65 ps • Low-Power Alternative for the MC100EP16 • Low 100-ps (Maximum) Part-to-Part Skew • 25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Input Voltage Range • Inputs Electrically Compatible With LVPECL,
CML, and LVDS Signal Levels • 3.