Datasheet4U Logo Datasheet4U.com

SN54CDC341 - 1-LINE TO 8-LINE CLOCK DRIVER

Description

The SN54CDC341 is a high-performance clockdriver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution.

Through the use of the control pins (1G and 2G), the outputs can be placed in a low state regardless of the A input.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
SN54HC595J 16-bit bus transceiver and transparant D-type latch nexperia
SN54LS00 QUAD 2-INPUT NAND GATE Motorola Inc
SN54LS01 QUAD 2-INPUT NAND GATE Motorola Inc
SN54LS02 QUAD 2-INPUT NOR GATE Motorola Inc
SN54LS03 QUAD 2-INPUT NAND GATE Motorola Inc

Other Datasheets by Texas Instruments

Part Number Description
SN54CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
SN54CBT16209 18-BIT FET BUS-EXCHANGE SWITCHES
SN54CBT16212A 24-BIT FET BUS-EXCHANGE SWITCHES
SN54CBT16244 16-BIT FET BUS SWITCHES
SN54CBT3383 10-Bit Bus-Exchange Switch

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SN54CDC341 1-LINE TO 8-LINE CLOCK DRIVER D Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications D TTL-Compatible Inputs and Outputs D Distributes One Clock Input to Eight Outputs D Distributed VCC and Ground Pins Reduce Switching Noise D High-Drive Outputs (– 48-mA IOH, 48-mA IOL) D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D Package Options Include Ceramic Flatpacks (W), Ceramic Chip Carriers (FK), and Ceramic (J) 300-mil DIPS SGAS005A – MARCH 1996 – REVISED JULY 1997 J OR W PACKAGE (TOP VIEW) VCC 1G 2G A P0 P1 VCC 2Y4 2Y3 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 1Y1 18 1Y2 17 GND 16 1Y3 15 1Y4 14 GND 13 2Y1 12 2Y2 11 GND FK PACKAGE (TOP VIEW) 2G 1G VCC VCC 1Y1 description The SN54CDC341 is a high-performance cl
Published: |