DS99R101 deserializer equivalent, 3-40mhz dc-balanced 24-bit lvds serializer / deserializer.
1
*2 3 MHz
–40 MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions
* User Selectable Clock Edge for Parallel Data on Both Transmitt.
* LOCK Output Flag to Ensure Data Integrity at Receiver Side
* Balanced TSETUP/THOLD Between RCLK and RDATA on R.
The DS99R101/DS99R102 Chipset translates a 24bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24bit bus over PCB traces and cable by elimina.
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