DS99R101 deserializer equivalent, (ds99r101 / ds99r102) 3-40mhz dc-balanced 24-bit lvds serializer and deserializer.
* 3 MHz
–40 MHz clock embedded and DC-Balancing 24:1
and 1:24 data transmissions Transmitter and Receiver
* User selectable clock edge for paralle.
LOCK output flag to ensure data integrity at Receiver side Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side.
The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by elimi.
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