DS90C124 serializer/deserializer equivalent, 5-mhz to 35-mhz dc-balanced 24-bit fpd-link ii serializer/deserializer.
*1 5-MHz to 35-MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions
* User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS O.
* LOCK Output Flag to Ensure Data Integrity at Receiver Side
* Balanced TSETUP and THOLD Between RCLK and RDATA .
The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over ca.
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