CDCM1804 divider equivalent, 1:3 lvpecl clock buffer + additional lvcmos output and programmable divider.
* Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output
* Programmable Output Divider for Two LVP.
for LVPECL Outputs; 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
* VCC Range 3 V
&nb.
The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCM1804 is specifically designed for driving 50-Ω transm.
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 2.19MB)