CDCF5801A multiplier equivalent, clock multiplier.
* Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8
* Fail-Safe Power Up Initialization
* Programmable Bidirectional Delay Steps of
1.3 mUI
* Output Frequency R.
* Video Graphics
* Gaming Products
* Datacom
* Telecom
* Noise Cancellation Created by FPGAs
DBQ PAC.
The CDCF5801A provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising edge on the DLYCTRL pin the CLKO.
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