CDCF2510 driver equivalent, 3.3-v phase-lock loop clock driver.
D Distributes One Clock Input to One Bank of
10 Outputs
D Output Enable Pin to Enable/Disable All 10
Outputs
D External .
The CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for.
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