CDC351I driver equivalent, 1-line to 10-line clock driver.
* Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
* Operates at 3.3-V VCC
* LVTTL-Compatible Inputs and Outputs
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* Operates at 3.3-V VCC
* LVTTL-Compatible Inputs and Outputs
* Supports Mixed-Mode Signal Operation (5-V In.
The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance state. The CDC351 operates at nomi.
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