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CDC351 - 1-Line To 10-Line Clock Driver

General Description

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution.

The output-enable (OE) input disables the outputs to a high-impedance state.

The CDC351 operates at nominal 3.3-V VCC.

Key Features

  • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.ti.com CDC351. CDC351I 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS441D – FEBRUARY 1994 – REVISED OCTOBER 2003 FEATURES • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications • Operates at 3.3-V VCC • LVTTL-Compatible Inputs and Outputs • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.