3 Description
* LSTTL input logic compatible
  – VIL(max) = 0.8 V, VIH(min) = 2 V
* CMOS input logic compatible
  – II ≤ 1 µA at VOL.

This device contains four independent 2-input AND gates. Each gate performs the Boolean function Y = A
* B in posit.

* LSTTL input logic compatible
  – VIL(max) = 0.8 V, VIH(min) = 2 V
* CMOS input logic compatible
  – II ≤ 1 µA at VOL, VOH
* Buffered inputs
* 4.5 V to 5.5 V operation
* Wide operating temperature ran.

CD74HCT00

CD74HCT00E

CD74HCT00M

CD74HCT02

CD74HCT03

CD74HCT04

CD74HCT10

CD74HCT107

CD74HCT109

CD74HCT10E

CD74HCT10M

CD74HCT11

CD74HCT112

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