* LSTTL input logic compatible
  – VIL(max) = 0.8 V, VIH(min) = 2 V
* CMOS input logic compatible
  – II ≤ 1 µA at VOL, VOH
* Buff.

* Alarm / tamper detect circuit
* S-R latch 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 3 Description Thi.

This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A
* B in positive logic. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) CD74HCT00M SOIC (14) 8.65 mm × 3.90 mm CD74HCT00E PD.

CD74HCT00

CD74HCT00M

CD74HCT02

CD74HCT03

CD74HCT04

CD74HCT08

CD74HCT10

CD74HCT107

CD74HCT109

CD74HCT10E

CD74HCT10M

CD74HCT11

CD74HCT112

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