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• Inputs Are TTL-Voltage Compatible • Contains Four Flip-Flops with Double-Rail
Outputs
• Clock Enable Latched to Avoid False
Clocking
• Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
• Flow-Through Architecture to Optimize
PCB Layout
• Center-Pin VCC and GND Configurations to
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
• Package Options Include Plastic Small
Outline Packages, and Standard Plastic
300-mil DIPs
74ACT11379 QUAD DĆTYPE FLIPĆFLOP
WITH CLOCK ENABLE
SCAS103 − JANUARY 1990 − REVISED APRIL 1993
DW OR N PACKAGE
(TOP VIEW)
1Q 2Q 2Q GND GND GND GND 3Q 3Q 4Q
1 2 3 4 5 6 7 8 9 10
20 1Q 19 CLKEN 18 1D 17 2D 16 VCC 15 VCC 14 3D
13 4D
12 CLK
11 4Q
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74ACT11379 Datasheet
