A3S56D30FTP Key Features
- Vdd=VddQ=2.5V+0.2V (-4, -5E, -5)
- Double data rate architecture ; two data transfers per clock cycle
- Bidirectional , data strobe (DQS) is transmitted/received with data
- Differential clock input (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
- mands entered on each positive CLK edge
- Data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0 , BA1 (Bank Address)
- /CAS latency
- 2.0 / 2.5 / 3.0 / 4.0 (programmable)