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A3R12E40CBF - 512Mb DDRII Synchronous DRAM

Download the A3R12E40CBF datasheet PDF (A3R12E30CBF included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 512mb ddrii synchronous dram.

Features

  • Double-data-rate architecture; two data transfers per clock cycle.
  • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
  • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
  • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
  • Differential clock inputs (CK and /CK).
  • DLL aligns DQ and DQS transitions with CK transi.

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Note: The manufacturer provides a single datasheet file (A3R12E30CBF-Zentel.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number A3R12E40CBF
Manufacturer Zentel
File Size 1.42 MB
Description 512Mb DDRII Synchronous DRAM
Datasheet download datasheet A3R12E40CBF Datasheet

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Full PDF Text Transcription

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A3R12E30CBF A3R12E40CBF 512Mb DDRII Synchronous DRAM 512Mb DDRII SDRAM Specification A3R12E30CBF A3R12E40CBF Zentel Electronics Corp. Revision 1.2 Sep., 2013 A3R12E30CBF A3R12E40CBF 512Mb DDRII Synchronous DRAM Specifications • Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks (A3R12E30CBF) ⎯ 8M words × 16 bits × 4 banks (A3R12E40CBF) • Package ⎯ 60-ball FBGA(μBGA) (A3R12E30CBF) ⎯ 84-ball FBGA(μBGA) (A3R12E40CBF) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Data rate: 1066Mbps/800Mbps(max.
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