A3R1GE4EGF Datasheet 1Gb DDRII SDRAM

Manufacturer: Zentel

A3R1GE4EGF 1gb ddrii sdram by Zentel - Datasheet Preview

Datasheet Details

Part number	A3R1GE4EGF
Manufacturer	Zentel
File Size	1.64 MB
Description	1Gb DDRII SDRAM
Datasheet	A3R1GE4EGF Datasheet

Overview

A3R1GE4EGF 1Gb DDRII Synchronous DRAM 1Gb DDRII SDRAM Specification A3R1GE4EGF Zentel Electronics Corp.

Revision 1.0 Apr., 2010 Specifications • Density: 1G bits • Organization ⎯ 8M words × 16 bits × 8 banks (A3R1GE4EGF) • Package ⎯ 84-ball FBGA(μBGA) (A3R1GE4EGF) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Data rate: 800Mbps/667Mbps (max.) ⎯ 800Μbps/667Mbps(max) • 2KB page size (A3R1GE4EGF) ⎯ Row address: A0 to A12 ⎯ Column address: A0 to A9 • Eight internal banks for concurrent operation • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • Burst type (BT): ⎯ Sequential (4, 8) ⎯ Interleave (4, 8) • /CAS Latency (CL): 3, 4, 5, 6 • Precharge: auto precharge option for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period 7.8μs at 0°C ≤ TC ≤ +85°C 3.

Key Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

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