900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






Zentel

A3R12E30DBF Datasheet Preview

A3R12E30DBF Datasheet

512Mb DDRII SDRAM

No Preview Available !

A3R12E30DBF
A3R12E40DBF
512Mb DDRII Synchronous DRAM
512Mb DDRII SDRAM Specification
A3R12E30DBF
A3R12E40DBF
Zentel Electronics Corp.
Revision 1.1
Nov., 2015




Zentel

A3R12E30DBF Datasheet Preview

A3R12E30DBF Datasheet

512Mb DDRII SDRAM

No Preview Available !

A3R12E30DBF
A3R12E40DBF
512Mb DDRII Synchronous DRAM
Specifications
Features
Density: 512 bits
Organization
16M words × 8 bits × 4 banks (A3R12E30DBF)
8M words × 16 bits × 4 banks (A3R12E40DBF)
Package
60-ball FBGA(μBGA) (A3R12E30DBF)
84-ball FBGA(μBGA) (A3R12E40DBF)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Data rate: 1066Mbps/800Mbps (max.)
1KB page size (A3R12E30DBF)
Row address: A0 to A13
Column address: A0 to A9
2KB page size (A3R12E40DBF)
Row address: A0 to A12
Column address: A0 to A9
Four internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
/CAS Latency (CL): 3, 4, 5, 6, 7
Precharge: auto Precharge option for each burst
access
Driver strength: normal/weak
Low self-refresh current parts are available (8EPH)
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8μs at TC+85°C
3.9μs at TC+85°C
Industrial grade compliant with AEC-Q100 grade3
Automotive grade compliant with AEC-Q100 grade2
Operating case temperature range
TC = 0°C to +85°C (Commercial grade)*
TC = -40°C to +95°C (Industrial grade)*
TC = -40°C to +105°C (Automotive grade)*
Double-data-rate architecture; two data transfers per clock
cycle
The high-speed data transfer is realized by the 4 bits
prefect pipelined architecture
Bi-directional differential data strobe (DQS and /DQS) is
transmitted/received with data for capturing data at the
receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die-Termination for better signal quality
Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
Off-Chip Driver (OCD) impedance adjustment is not
supported
Note: Refer to operating temperature condition on page 5 for
details
Zentel Electronics Corporation reserve the right to change products or specification without notice.
Revision 1.1
Page 1 / 71
Nov., 2015


Part Number A3R12E30DBF
Description 512Mb DDRII SDRAM
Maker Zentel
Total Page 30 Pages
PDF Download

A3R12E30DBF Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 A3R12E30DBF 512Mb DDRII SDRAM
Zentel





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy