SP8400 Datasheet - Zarlink Semiconductor

SP8400 Very Low Phase Noise Synthesiser Divider

synthesiser divider The divider is based on a divide by 8/9 modulus prescaler, and a 12 stage control counter. This gives minimum fractional * N division ratio of 64 (56 for general division), and a maximum division ratio of 4103. The inputs to the control counter are TTL/CMOS compatible. T.

www.DataSheet4U.com SP8400 Very Low Phase Noise Synthesiser Divider September 2005 The SP8400 is a very low phase noise programmable divider which is based on a divide by 8/9 dual modulus prescaler and a 12 stage control counter. This gives a minimum division ratio of 56 (64 for fractional - N synthesis applications), and a maximum division ratio of 4103. Special circuit techniques have been used to reduce the phase noise considerably below that produced by standard dividers.The data inputs a.

SP8400 Features

* I Very low Phase Noise (Typically -156dBc/Hz at 1kHz offset) I Supply Voltage 5V M2 M1 M0 VCC +5V GND CLOCK INPUT CLOCK INPUT CLOCK INPUT CLOCK INPUT GND VCC +5V VCC +5V GND A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 M3 M4 M5 M6 M7 M8 N/C OUTPUT OUTPUT N/C VCC

SP8400 Datasheet (409.42 KB)