CLA60000 Key Features
- Channel less arrays to 110,000 gates 1.4 micron dual layer metal silicon CMOS process Typical Gate Delays of 700ps (NAND
- CLA60000 Chip Microplot All CLA60000 arrays have the same construction. A core of unmitted transistors is arranged for o
- the absence of discrete wiring channels increases flexibility, reduces track capacitance whilst significantly increasing t