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Channel less CMOS Gate Arrays
This new family of gate arrays uses many innovative
techniques to achieve 110K gates per chip with
system clock speeds of up to 70MHz. The
combination of high speed, high gate complexity and
low power operation places Zarlink Semiconductor
at the forefront of ASIC capability.
The CLA60000 gate array family is Zarlink
Semiconductor’s ﬁfth-generation CMOS gate array
product. These arrays allow even higher integration
densities at enhanced system clock rates as need for
many of today’s system applications.
The largest array in the family at 110K gates offers a
tenfold increase in raw gate availability then
channelled gate arrays. In addition, many new
designs features have been incorporated such as
analog functionality, slew rate output control, and
intermediate I/O buffering for optimum data transfer
through peripheral cells.
Also, the low-power characteristics of Zarlink
Semiconductor CMOS processing have been
incorporated in these arrays, easing the thermal
management problems associated with complex
designs of 20,000 gates and above.
• Channel less arrays to 110,000 gates
• 1.4 micron dual layer metal silicon CMOS
• Typical Gate Delays of 700ps (NAND2)
• Comprehensive cell library including microcells,
macrocells, and paracells
• Power distribution optimized for maximum noise
• Slew controlled outputs with up to 24mA drivers
• Fully supported by design software (PDS2) and
• Very high latch up immunity
Figure 1 - CLA60000 Chip Microplot
All CLA60000 arrays have the same construction. A
core of uncommitted transistors is arranged for
optimum connection as logic functions and
surrounded by uncommitted peripheral (I/O) circuitry.
The channel less array architecture is an important
feature - the absence of discrete wiring channels
increases ﬂexibility, reduces track capacitance whilst
signiﬁcantly increasing transistor sizes for improved
The construction of the basic building blocks have
been planned to support basic logic functions, macro
functions, and core memory functions (RAM and
ROM) with high routability. Logic programmability is
given by dual level metal, with interconnecting vias,
plus a forth level of programmability (contacts).
The overall architecture of these gate arrays has
been designed to exploit many new and emerging
developments in CAD tools. Increasing demands are
now being made for design tools which are faster,
easier to use, and more accurate. The Zarlink
Semiconductor Design System (PDS2) allows full
control over all aspects of design including logic
capture, simulation and layout.