Datasheet4U Logo Datasheet4U.com

CLA60000 - Channel Less CMOS Gate Arrays

General Description

Th e CLA60000 gate arra y f amily i s Zarlink Semiconductor’s fifth-generation CMOS gate array product.

These arrays allow even higher integration densities at enhanced system clock rates as need for many of today’s system applications.

Key Features

  • have been incorporated such as analog functionality, slew rate output control, and intermediate I/O buffering for optimum data transfer through peripheral cells. Also, the low-power characteristics of Zarlink Semiconductor CMOS processing have been incorporated in these arrays, easing the thermal management problems associated with complex designs of 20,000 gates and above. Features.
  • Channel less arrays to 110,000 ga.

📥 Download Datasheet

Datasheet Details

Part number CLA60000
Manufacturer Zarlink Semiconductor
File Size 1.58 MB
Description Channel Less CMOS Gate Arrays
Datasheet download datasheet CLA60000 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
( DataSheet : www.DataSheet4U.com ) CLA60000 Series Channel less CMOS Gate Arrays This new family of gate arrays uses many innovative techniques to achieve 110K gates per chip with system clock speeds of up to 70MHz. The combination of high speed, high gate complexity and low power operation places Zarlink Semiconductor at the forefront of ASIC capability. General Description Th e CLA60000 gate arra y f amily i s Zarlink Semiconductor’s fifth-generation CMOS gate array product. These arrays allow even higher integration densities at enhanced system clock rates as need for many of today’s system applications. The largest array in the family at 110K gates offers a tenfold increase in raw gate availability then channelled gate arrays.