CLA60000 Overview
Th e CLA60000 gate arra y f amily i s Zarlink Semiconductor’s fifth-generation CMOS gate array product. These arrays allow even higher integration densities at enhanced system clock rates as need for many of today’s system applications. The largest array in the family at 110K gates offers a tenfold increase in raw gate availability then channelled gate arrays.
CLA60000 Key Features
- Channel less arrays to 110,000 gates 1.4 micron dual layer metal silicon CMOS process Typical Gate Delays of 700ps (NAND
- CLA60000 Chip Microplot All CLA60000 arrays have the same construction. A core of unmitted transistors is arranged for o
- the absence of discrete wiring channels increases flexibility, reduces track capacitance whilst significantly increasing t