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CLA200 - CMOS Gate Arrays

Features

  • 0.35µm drawn Channel Length Three (CLT) and Four (CLQ) layer metal options Automated base array constructor for optimised arrays with up to 3 million gates Low Power, 0.4µ W/MHz/Gate at 3V (2-input NAND with two loads) 135ps gate delay for 2-input NAND with two loads (3V) High density staggered pad ring Wide range of package options including QFP & BGA Characterised for operation from 1.

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Datasheet Details

Part number CLA200
Manufacturer Zarlink Semiconductor
File Size 197.43 KB
Description CMOS Gate Arrays
Datasheet download datasheet CLA200 Datasheet

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( DataSheet : www.DataSheet4U.com ) CLA200 Series CMOS Gate Arrays Advance Information DS4812 ISSUE 1.3 July 1997 INTRODUCTION The CLA200 Series Arrays from Zarlink Semiconductor offer designers the capability to integrate designs of more than 2 million gates. There are 14 fixed arrays optimised for low to medium complexity designs ranging from 11K used gates up to 628K used gates. For larger designs optimised arrays can be built with up to 3 million available gates. Using automated gate array base constructor software, a tailor made optimised gate array can be built to customers requirements which gives designers the ability to specify the optimum die size whilst retaining the benefits of standard gate arrays.
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