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Zarlink Semiconductor

CLA200 Datasheet Preview

CLA200 Datasheet

CMOS Gate Arrays

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CLA200 Series
CMOS Gate Arrays
Advance Information
INTRODUCTION
The CLA200 Series Arrays from Zarlink Semiconductor offer
designers the capability to integrate designs of more than 2
million gates. There are 14 fixed arrays optimised for low to
medium complexity designs ranging from 11K used gates up
to 628K used gates. For larger designs optimised arrays can
be built with up to 3 million available gates. Using automated
gate array base constructor software, a tailor made optimised
gate array can be built to customers requirements which gives
designers the ability to specify the optimum die size whilst
retaining the benefits of standard gate arrays. Utilising a gate
array architecture allows the base arrays to be pre-
manufactured enabling gate array prototype lead time to be
offered.
Supported with high quality design kits for a range of industry
standard CAE tools, the CLA200 Series provide customers
with a low risk, low cost solution and fast time to market.
FEATURES
• 0.35µm drawn Channel Length
• Three (CLT) and Four (CLQ) layer metal options
• Automated base array constructor for optimised arrays
with up to 3 million gates
• Low Power, 0.4µW/MHz/Gate at 3V (2-input NAND with
two loads)
• 135ps gate delay for 2-input NAND with two loads (3V)
• High density staggered pad ring
• Wide range of package options including QFP & BGA
• Characterised for operation from 1.8V to 3.6V
• 2V and 3.3V I/O capability on the same device
• 5V tolerant inputs, outputs and bidirectionals
• Accurate delay modelling for gates and tracks with sign
off quality CAE design libraries for QuickSim II and
Verilog-XL
• VITAL Sign off with Synopsys VSS Simulator
• CAD libraries optimised for synthesis
• Methodologies for low clock skew
• Full set of I/O cells for direct pad synthesis
• Variable output slew rates for low noise
• IDDQ Testing
BENEFITS
• Fast Customer Time To Market
- Direct sign-off on Industry Standard CAE tools
- Comprehensive Industry Standard CAE tools
- SystemBuilder™ megacell libraries
- World-wide design center support
- Reliable prototype and production delivery
- Dual silicon sources
DS4812
ISSUE 1.3
July 1997
• Cost -effective solutions
- Optimised silicon architecture for high density silicon
utilisation
- ISO9001 Factory with Statistical process control for
optimum yield
FIXED ARRAY SIZES
Available Available
Pads
Gates
CLA201
CLA202
CLA203
CLA204
CLA205
CLA206
CLA207
CLA208
CLA209
CLA210
CLA211
CLA212
CLA213
CLA214
48
64
80
100
128
144
160
176
208
240
272
304
328
352
17,860
30,012
45,300
68,736
109,980
137,812
168,780
202,884
280,500
370,660
473,364
588,612
683,280
785,004
Usable
Gates
TLM
10,700
18,000
27,200
41,200
66,000
82,700
101,300
121,700
168,300
222,400
284,000
353,200
410,000
471,000
Usable
Gates
QLM
14,300
24,000
36,200
55,000
88,000
110,200
135,000
162,300
224,400
296,500
378,700
470,900
546,600
628,000
OPTIMISED ARRAYS
The following table illustrates examples of possible compiled
array sizes.
Available Available
Pads
Gates
Usable
Gates
TLM
Usable
Gates
QLM
CLA2xx
400
989,740 590,000
790,000
CLA2xx
552
1,879,776 1,100,000 1,500,000
CLA2xx
700
3,018,424 1,800,000 2,400,000
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Zarlink Semiconductor

CLA200 Datasheet Preview

CLA200 Datasheet

CMOS Gate Arrays

No Preview Available !

CLA200 Series Advance Information
ARRAY ARCHITECTURE
The CLA200 Series gate array family is based on a sea of
gates array architecture. The arrays consist of a core of
transistors, overlaid with a core power supply grid, ringed by
three concentric pairs of VDD and GND supply rail. The
OPVDD rail can be split to form an extra VDD rail named split
supply VDD (SSVDD) to allow mixed voltages interfaces on
the same device. The outermost area of the die has pads for
I/O and power supplies.
Each array has a number of preferred pads designated for
power supply, This allows the use of a generic probe card to
reduce cost and allow rapid prototype turnaround.
Connections within the array are made using three or four
layers of metal. Each pad has one I/O location associated with
it.
CORE ARCHITECTURE
The core area consists of a dense array of core cells. Each
core cell contains four transistors, two NMOS and two PMOS,
whose sizes have been optimised for high density and low
power. These are built from one structure consisting of a
shared central source/drain region with independently
available polysilicon gates. This core cell layout has been
designed to allow very efficient metal interconnections
including over-cell routing resulting in high utilisation. The core
architecture also allows highly efficient register file RAM to be
implemented.
CELL LIBRARIES
The CLA200 Series is supported by a comprehensive cell
library which is optimised for synthesis and includes basic
logic gates, oscillators and memories. In addition a range of
ready made system Macro functions such as a UART is also
available.
Core Microcells
A wide range of core microcells are available including basic
logic cells, combinatorial logic, latches and D- Type Flip-Flops.
The basic logic cells, such as inverters, NAND and NOR gates
are available with a choice of drive strengths allowing
designers to make trade-offs between speed, power and
silicon area. A range of D-Type flip-flops is also available
including versions with multiplexers to facilitate Scan path
testing.
2


Part Number CLA200
Description CMOS Gate Arrays
Maker Zarlink Semiconductor
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