* Advanced, high-performance, FPGA Logic
* Real 6-input look-up table (LUT) technology
* Dual LUT5 (5-input LUT) option
* LUT/dual flip-flop pair for app.

requiring rich register mix
* Improved routing efficiency
* 64-bit (or 32 x 2-bit) distributed LUT RAM option

Virtex®-6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1 slices, enhance.

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