WCSS0232V1P ram equivalent, 64k x 32 synchronous-pipelined cache ram.
* Supports 133-MHz bus for Pentium® and PowerPC™ operations with zero wait states
* Fully registered inputs and outputs for pipelined operation
* 64K x 32 com.
The WCSS0232V1P is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.
Logic Block Diagram
CLK ADV ADSC ADSP A[15:0] GW BWE BW 3 BW2 BW1
MODE (A[1:0]) 2 BURST Q0 CE COUNTER.
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