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TC58NVG6T2FTA00 - 64 GBIT (8G X 8 BIT) CMOS NAND E2PROM

General Description

The TC58NVG6T2FTA00 is a single 3.3 V 64 Gbit (79,054,700,544 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192  1024) bytes  258 pages 4156 blocks.

Key Features

  • Organization Memory cell array Register Page size Block size.
  • TC58NVG6T2FTA00 9216  1047.1171875K  8 9216  8 9216 bytes (2064K  258K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Multi Page Program, Multi Block Erase, Multi Page Read Mode control Serial input/output Command control Number of valid blocks Min 4000 blocks Max 4156 blocks Power supply VCC  2.7 V to 3.6 V Access time Cell array to register Serial Read Cycle Program/Erase time Auto Page.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TOSHIBA CONFIDENTIAL TENTATIVE TC58NVG6T2FTA00 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 64 GBIT (8G  8 BIT) CMOS NAND E PROM (Triple-Level-Cell) DESCRIPTION The TC58NVG6T2FTA00 is a single 3.3 V 64 Gbit (79,054,700,544 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192  1024) bytes  258 pages 4156 blocks. The device has four 9216-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 9216-byte increments. The Erase operation is implemented in a single block unit (2064 Kbytes  258 Kbytes:9216 bytes x 258 pages).