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TC58NVG5D2ELA48 - 32 GBIT (4G x 8 BIT) CMOS NAND E2PROM

Description

The TC58NVG5D2 is a single 3.3 V 32 Gbit (36,393,025,536 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 376) bytes × 128 pages × 4148 blocks.

Features

  • Organization Memory cell array Register Page size Block size TC58NVG4D2E 8568 × 518.5K × 8 8568 × 8 8568 bytes (1M + 47 K) bytes.
  • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Mullti Page Read.
  • Mode control Serial input/output Command control.
  • Number of valid blocks Min 3936 blocks Max 4148 blocks.
  • Power supply VCC = 2.7 V to 3.6 V.
  • Access time C.

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Datasheet preview – TC58NVG5D2ELA48

Datasheet Details

Part number TC58NVG5D2ELA48
Manufacturer Toshiba
File Size 575.02 KB
Description 32 GBIT (4G x 8 BIT) CMOS NAND E2PROM
Datasheet download datasheet TC58NVG5D2ELA48 Datasheet
Additional preview pages of the TC58NVG5D2ELA48 datasheet.

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Full PDF Text Transcription

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TOSHIBA CONFIDENTIAL TC58NVG5D2ELA48 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM (Multi-Level-Cell) DESCRIPTION The TC58NVG5D2 is a single 3.3 V 32 Gbit (36,393,025,536 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 376) bytes × 128 pages × 4148 blocks. The device has two 8568-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 8568-byte increments. The Erase operation is implemented in a single block unit (1 Mbytes + 47 Kbytes: 8568 bytes × 128 pages). The TC58NVG5D2 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.
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