TC58NVG5D2ELA48 Datasheet | Toshiba

DESCRIPTION The TC58NVG5D2 is a single 3.3 V 32 Gbit (36,393,025,536 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 376) bytes × 128 pages × 4148 blocks. The device has two 8568-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 8568-byte increments. The Erase operation is implemented in a single block unit (1 Mbytes + 47 Kbytes: 8568 bytes × 128 pages). The TC58NVG5D2 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for mand inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES - Organization Memory cell array Register Page size Block size TC58NVG4D2E 8568 × 518.5K × 8 8568 × 8 8568 bytes (1M + 47 K) bytes - Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Mullti Page Read - Mode control Serial input/output mand control - Number of valid blocks Min 3936 blocks Max 4148 blocks - Power supply VCC = 2.7 V to 3.6 V - Access time Cell array to register 200 µs max Serial Read Cycle 25 ns min - Program/Erase time Auto Page Program Auto Block Erase 1600 µs/page typ. 4.5 ms/block typ. - Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby TBD ( 65 to 70) m A max. TBD ( 65 to 70)m A max. TBD ( 65 to 70)m A max. 100µA max - Package (Weight: g typ.) - FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND MENTS (17). 24 bit ECC for each 1024 bytes is required. 1 2008-07-18C TOSHIBA CONFIDENTIAL PIN ASSIGNMENT (TOP VIEW) Index A B C D E F G H J K L M N PIN NAMES I/O1-1 ~ I/O8 CE WE RE CLE ALE WP RY/BY GND...