TC58NVG0S3HBAI4 Datasheet | Toshiba

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1G BIT (128M  8 BIT) CMOS NAND E PROM DESCRIPTION The TC58NVG0S3HBAI4 is a single 3.3V 1Gbit (1,140,850,688bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048  128) bytes  64 pages  1024blocks. The device has a 2176-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes  8 Kbytes: 2176 bytes  64 pages). The TC58NVG0S3HBAI4 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for mand inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. Features - Organization Memory cell array Register Page size Block size - - x8 2176  64K  8 2176  8 2176 bytes (128K  8K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy Mode control Serial input/output mand control Number of valid blocks Min 1004 blocks Max 1024 blocks Power supply VCC  2.7V to 3.6V Access time Cell array to register 25 s max Serial Read Cycle 25 ns min (CL=50p F) Program/Erase time Auto Page Program Auto Block Erase Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby 300 s/page typ. 2.5 ms/block typ. 30 m A max. 30 m A max 30 m A max 50 A max (Weight: 0.15 g typ.) - - - - - - - Package P-TFBGA63-0911-0.80CZ 8 bit ECC for each 512Byte is required. 2012-10-01C http://.. PIN ASSIGNMENT (TOP VIEW) 1 A B C D E F G H J K L M NC NC NC NC NC NC 2 NC 9 NC NC 10 NC NC VSS CLE NC NC NC NC NC I/O4 WE...