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Sony Semiconductor Electronic Components Datasheet

CXB1452Q Datasheet

VGA/SVGA/XGA digital data serial receiver

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CXB1452Q
VGA/SVGA/XGA digital data serial receiver
Features
• 1 chip receiver for serial transmission of 18bit color
VGA/SVGA/XGA picture
• On chip differential cable driver
• TTL/CMOS compatible interface
• Support 1 pixel/shiftclock mode & 2 pixel/shiftclock
mode
• +3.3V single power supply
• Low power consumption
• 80pin Plastic QFP Package
(Body size: 14mm × 14mm)
Block Digagram & Pin out
80 pin QFP (Plastic)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
TESTDT 61
PANEL1 62
PANEL0 63
CKMODE 64
CNTL3 65
CNTL2 66
CNTL1 67
VEEG 68
VCCG 69
VCCT 70
VEET 71
SFTCLK 72
HSYNC 73
VSYNC 74
VEEG 75
VCCG 76
CNTL0 77
BLU1 (5) 78
BLU1 (4) 79
VCCT 80
CDR
PLL
Cable
EQ
Serial
to
Parallell
Converter
Decoder
40 VCCT
39 GRN0 (0)
38 GRN0 (1)
37 GRN0 (2)
36 GRN0 (3)
35 GRN0 (4)
34 GRN0 (5)
33 VEEG
32 VCCG
31 VEET
30 VCCT
29 BLU0 (0)
28 BLU0 (1)
27 BLU0 (2)
26 VEEG
25 VCCG
24 BLU0 (3)
23 BLU0 (4)
22 BLU0 (5)
21 VEET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Fig. 1. Block Diagram & Pin out
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97937-PS


Sony Semiconductor Electronic Components Datasheet

CXB1452Q Datasheet

VGA/SVGA/XGA digital data serial receiver

No Preview Available !

CXB1452Q
Pin List
Power/Ground
Pin Name
Pin Number
Descriptions
VCCT
VEET
VCCG
VEEG
VCCA
VEEA
VEES
10, 20, 30, 40, 48, 70, 80
1, 11, 21, 31, 41, 49, 71
25, 32, 69, 76
26, 33, 68, 75
56
57
58
TTL power surpply , should be connected to 3.3V ± 5%
TTL ground, connected to 0V
Logical core power surpply, connected to 3.3V ± 5%
Logical core ground, connected to 0V
Analog power surpply, connected to 3.3V ± 5%
Analog ground, connected to 0V
Analog substrate, connected to 0V
Digital Signals
Pin Name
Pin Number
SFTCLK
72
RED1 (5 to 0) 14, 15, 16, 17, 18, 19
GRN1 (5 to 0) 6, 7, 8, 9, 12, 13
BLU1 (5 to 0) 78, 79, 2, 3, 4, 5
RED0 (5 to 0) 42, 43, 44, 45, 46, 47
GRN0 (5 to 0) 34, 35, 36, 37, 38, 39
BLU0 (5 to 0) 22, 23, 24, 27, 28, 29
HSYNC
73
VSYNC
74
CNTL (3 to 0) 65, 66, 67, 77
PANEL (1, 0) 62, 63
CKMODE
64
LOS
50
SDATAP/N 52, 53
REFRQP/N 51, 54
Type
Descriptions
TTL out Shift clock, for the data fetch at falling or rising edge
TTL out
Pixel data input in 1 pixcel/sftclk mode
2nd pixel data input in 2 pixel/sftclk mode
TTL out
High fixed in 1 pixcel/sftclk mode
1st pixel data input in 2 pixel/sftclk mode
TTL out Hsync data
TTL out Vsync data
TTL out Control data
TTL in Panel mode select switch
TTL in Clock mode select switch
TTL out Los of signal
Rx Serial input
Rx Refclk request
Special
Pin Name Pin Number
Descriptions
TESTSB/DT 55, 61
Polarity control of SFTCLK & TEST under fablication
LPFA/B
59, 60
External loop filter
–2–


Part Number CXB1452Q
Description VGA/SVGA/XGA digital data serial receiver
Maker Sony Corporation
Total Page 13 Pages
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