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SI53366 - LVCMOS Fanout Clock Buffers

Download the SI53366 datasheet PDF. This datasheet also covers the SI53360 variant, as both devices belong to the same lvcmos fanout clock buffers family and are provided as variant models within a single manufacturer datasheet.

Description

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4 2.2 Input Mux

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Features

  • Low additive jitter: 120 fs rms.
  • Built-in LDOs for high PSRR performance.
  • Up to 12 LVCMOS Outputs from LVCMOS inputs.
  • Frequency range: dc to 200 MHz.
  • Multiple configuration options.
  • Dual Bank option.
  • 2:1 Input MUX option.
  • RoHS compliant, Pb-free.
  • Temperature range:.
  • 40 to +85 °C VDD Power Supply Filtering CLK0 CLK1 CLK_SEL 0 1 8 6 6 VDDO (Si53361 only) OEA 8 Outputs Si53360/61 VDDOA OEA 6 Outputs 6.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SI53360-SiliconLaboratories.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
Si53360 LVCMOS Fanout Clock Buffers Skyworks
Si53361 LVCMOS Fanout Clock Buffers Skyworks
Si53362 LVCMOS Fanout Clock Buffers Skyworks
Si53365 LVCMOS Fanout Clock Buffers Skyworks
Si53301 Ultra-Low Additive Jitter Fanout Clock Buffers Skyworks

Other Datasheets by Silicon Laboratories

Part Number Description
SI53360 LVCMOS Fanout Clock Buffers
SI53361 LVCMOS Fanout Clock Buffers
SI53362 LVCMOS Fanout Clock Buffers
SI53365 1:8 LOW JITTER CMOS CLOCK BUFFER
SI533 DUAL FREQUENCY CRYSTAL OSCILLATOR

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Si53360/61/62/65 Data Sheet Low-Jitter, LVCMOS Fanout Clock Buffers with up to 12 outputs and Frequency Range from dc to 200 MHz The Si53360/61/62/65 family of LVCMOS fanout buffers is ideal for clock/data distribution and redundant clocking applications. The family utilizes Silicon Labs advanced CMOS technology to fanout clocks from dc to 200 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. Built-in LDOs deliver high PSRR performance and eliminates the need for external components simplifying low jitter clock distribution in noisy environments. The CMOS buffers are available in multiple configurations with 8 outputs (Si53360/61/65), or dual banks of 6 outputs each (Si53362).
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