K4X51163PE-LE Datasheet | Samsung Semiconductor

FEATURES - VDD/VDDQ = 1.8V/1.8V - Double-data-rate architecture; two data transfers per clock cycle - Bidirectional data strobe(DQS) - Four banks operation - Differential clock inputs(CK and CK) - MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) - EMRS cycle with address key programs - Partial Array Self Refresh ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 ) - Internal Temperature pensated Self Refresh - All inputs except data & DM are sampled at the positive going edge of the system clock(CK). .. - Data I/O transactions on both edges of data strobe, DM for masking. - Edge aligned data output, center aligned data input. - No DLL; CK to DQS is not synchronized. - DM0 - DM3 for write masking only. - Auto refresh duty cycle - 7.8us for -25 to 85 °C Mobile DDR SDRAM 2. Operating Frequency DDR333 Speed @CL21) 83Mhz 166Mhz Speed @CL31) NOTE: 1) CAS Latency DDR266 83Mhz 133Mhz 3. Address configuration Organization 32Mx16 - DM is internally loaded to match DQ and DQS identically. Bank Address BA0,BA1 Row Address A0 - A12 Column Address A0 - A9 4. Ordering Information Part No. K4X51163PE-L(F)E/GC6 K4X51163PE-L(F)E/GC3 Max Freq. 166MHz(CL=3),83MHz(CL=2) 133MHz(CL=3),83MHz(CL=2) Interface LVCMOS Package 60FBGA Pb (Pb Free) - L(F)E : 60FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25 °C ~ 85 °C) - L(F)G : 60FBGA Pb(Pb Free), Low Power, Extended Temperature(-25 °C ~ 85 °C) - C6/C3 : 166MHz(CL=3) / 133MHz(CL=3) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information...