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K4X51163PC - 32M x16 Mobile-DDR SDRAM

General Description

Clock : CK and CK are differential clock inputs.

All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK.

Internal clock signals are derived from CK/CK.

Key Features

  • Mobile-DDR SDRAM.
  • 1.8V power supply, 1.8V I/O power.
  • Double-data-rate architecture; two data transfers per clock cycle.
  • Bidirectional data strobe(DQS).
  • Four banks operation.
  • 1 /CS.
  • 1 CKE.
  • Differential clock inputs(CK and CK).
  • MRS cycle with address key programs - CAS Latency ( 2, 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 Array ) - Output Driver St.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com K4X51163PC - L(F)E/G 32M x16 Mobile-DDR SDRAM FEATURES Mobile-DDR SDRAM • 1.8V power supply, 1.8V I/O power • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • 1 /CS • 1 CKE • Differential clock inputs(CK and CK) • MRS cycle with address key programs - CAS Latency ( 2, 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 ) • Internal Temperature Compensated Self Refresh • Deep Power Down Mode • All inputs except data & DM are sampled at the positive going edge of the system clock(CK). • Data I/O transactions on both edges of data strobe, DM for masking.