* VDD/VDDQ = 1.8V/1.8V
* Double-data-rate architecture; two data transfers per clock cycle
* Bidirectional data strobe(DQS)
* Four banks operation
* D.

where Product failure could result in loss of life or personal or physical harm, or any military or defense application,.

Symbol CK, CK Type Input Description Mobile DDR SDRAM Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Internal clock signals are .

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