Datasheet4U Logo Datasheet4U.com

K7P401822M - SRAM

Download the K7P401822M datasheet PDF. This datasheet also covers the K7P403622M variant, as both devices belong to the same sram family and are provided as variant models within a single manufacturer datasheet.

Description

Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ VDD Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable Asyn

Features

  • 128Kx36 or 256Kx18 Organizations.
  • 3.3V Core Power Supply.
  • LVTTL Input and Output Levels.
  • Differential, PECL Clock Inputs K, K.
  • Synchronous Read and Write Operation.
  • Registered Input and Registered Output.
  • Internal Pipeline Latches to Support Late Write.
  • Byte Write Capability(four byte write selects, one for each 9bits).
  • Synchronous or Asynchronous Output Enable.
  • Power Down Mode via ZZ Signal.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K7P403622M-Samsung.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
K7P401823B 128Kx36 & 256Kx18 SRAM Samsung semiconductor
K7P403623B 128Kx36 & 256Kx18 SRAM Samsung semiconductor
K7P161866A (K7P161866A / K7P163866A) 512Kx36 AND 1Mx18 Synchronous Pipelined SRAM Samsung semiconductor
K7P163866A (K7P161866A / K7P163866A) 512Kx36 AND 1Mx18 Synchronous Pipelined SRAM Samsung semiconductor
K7P321866M 1Mx36 & 2Mx18 SRAM Samsung semiconductor

Other Datasheets by Samsung Semiconductor

Part Number Description
K7P401822B SRAM
K7P403622B SRAM
K7P403622M SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
K7P403622M K7P401822M 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters. Rev. 0.2 Rev. 1.0 - Updated IDD, ISB and Input High Level. Updated tKHKL, tKLKH, tKHQX, tKHQX1 and AC Test Conditions. For JTAG, updated Vendor Definition and added tSVCH/tCHSX. - Final specification release Draft Date April, 1997 Remark Preliminary Preliminary Jan. 1998 Preliminary Dec. 1998 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications.
Published: |